samuraipizzacat29 wrote:rschnier wrote:Steve Jones wrote:Are c**p old Italian organs or Realistic MG-1's digital synths? They use digital dividers to get their note frequencies. Spooky.

Yes, in that case at least the tone generation part is digital.........hammond novachord has digital elements in it, even though it's implemented with tubes/vales!

I don't understand. This is a contradiction to what you previously wrote. if the divide-down circuit is the direct output (even though these are square waves) how can this be referred to as digital?

is the point that you're comparing/using the leading/trailing edges of a wave to control a flip flop and since this is a function the theory of which is digital in nature (it's a logic operation), that we're calling it a digital operation? Yet, if that's the output that we're hearing, then those waves are analog, no?

I'm asking because I'm genuinely confused now.

If that's what you're saying, then it provides further insight into what we call a DCO, because in that case I think we'd say that everything up to the switching operation is a digital operation. yet, because the switching operation creates a wave that is intended to be disseminated by our ears, that can be considered an analog signal. Even the switch itself is digital, but the output is analog. (just hashing it out in my brain and typing accordingly)

I would have considered the operation itself analog because it's a physical change. But if the operation is digital because you're analyzing a high/low state, then I can understand why that would be true. fun times.....

I thought someone might ask that, so during the day today I thought about how best to answer it. Here goes:

The divide-down circuit is digital because it has

**two discrete internal states**:

- A state where it's receptive to being reset, and
- A state where it's
**not** receptive to being reset.

Which state the circuit is in, is determined by whether its output voltage is

**less** than a certain "threshold" value, or

**greater** than that value. (Remember from the last discussion: a digital circuit is a kind of analog circuit in which we've

*assigned meaning to the circuit's states based on whether a parameter of the circuit -- usually its output voltage -- falls into one range or another range*.) Here, we've designed our circuit so that if its output voltage is

**less** than the threshold value, the circuit is

**not** receptive to being reset...while if the output voltage is

**greater** than the threshold value, the circuit

**is** receptive to being reset. Two ranges, two states. For simplicity, let's define the threshold value to be 50% of the high-limit voltage of the circuit. Furthermore, let's say that after being reset, the divider circuit's output voltage starts out at zero, then increases over time, and when the circuit is reset, the voltage drops back to zero again. (You can easily get this behavior by charging a capacitor with a controlled current -- it's exactly like filling up a glass of water from the faucet.)

Since the above was a mouthful, here's another way to imagine it. You have a drinking glass that you're filling with a stream of water from the faucet. Someone might tell you to dump the glass out at anytime, but you've decided that you're going to ignore them unless the glass is more than than half full of water. Again, two states:

- A state where you'll ignore the person telling you to dump the glass (it's less than half full) and
- A state where you'll dump the glass when they ask you to (greater than half full).

Still with me? OK, now let's talk about the waveform that we're feeding into this divider circuit. It's going "up and down" in voltage at a certain rate. For this example, let's say it goes from "zero voltage" to "high voltage" and back to "zero voltage" 100 times per second. If you fed that voltage into an amp and loudspeaker, you'd hear a tone at 100 Hz. Thus, the waveform goes from zero to high and then back to zero voltage in 0.01 seconds (1/100 of a second).

Now, let's say that our divider circuit is designed so it's going to take about 0.25 seconds -- the exact time is not important as long as it's more than 0.2 seconds -- to go from zero voltage to its maximum voltage (in other words, we're filling the drinking glass at a rate so the glass is full in about a quarter of a second).

OK. Now we feed the input waveform -- cycling at 100 times per second -- into the divider circuit. As mentioned before, the divider circuit's output voltage starts at zero and then increases so that it's at maximum in 0.25 seconds. (Filling the drinking glass from the faucet.)

After 0.1 seconds, the input waveform is going to be back at zero voltage. (It's gone from zero to high and back to zero voltage again, in 0.1 seconds.) But after 0.1 seconds, the divider circuit's output voltage is

*not going to be over 50% of max voltage yet* -- it takes 0.125 seconds for it to reach 50%. So the divider circuit ignores the request to "dump its glass of water" and does not reset its output voltage back to zero at this time.

OK, after 0.125 seconds, the divider circuit's output voltage has now increased to 50% of maximum voltage. At this point, the divider circuit has

**changed states** -- it's gone from "ignore reset request" state to "obey reset request" state. And again, this change of state is determined solely by whether the output voltage falls into one range vs. another -- under 50% of maximum vs. over 50% of maximum.

After 0.2 seconds, the input waveform is back at zero voltage again. The last time this happened (at 0.1 seconds), our divider circuit ignored this and let its output voltage keep increasing on its merry way. But now, the output voltage is

**over** 50% of maximum, which it wasn't before, and

**this time** the divider circuit

**obeys** the signal from the input waveform to reset its output voltage back to zero. The result of all this is that the output voltage of the divider has been made to go from zero to high voltage and back to zero again in

**0.2** seconds, exactly half the rate at which the input voltage of the divider has gone from zero to high voltage and back to zero again (0.1 seconds). Note that the divider would normally take 0.25 seconds for its output voltage to reach maximum and stop climbing, but by defining two distinct ranges for the output voltage and using those ranges -- states -- to determine whether we're going to obey a reset request or not, we've "synced" the two waveforms so that one cycles at exactly half the rate of the other. (That's why it doesn't matter whether the divider's normal min-to-max time is exactly 0.25 seconds or not -- anything over 0.2 seconds will do the job -- but we don't want it to be too far over 0.2 seconds.)

It's all about whether the circuit has multiple, discrete states or not.