Hi,
What I am trying to do is illustrated above.
There is a clock that is output from an external device that acts as a timing reference so that the FPGA can meet setup and hold times relative to that clock. What I am struggling with is to figure out what the timing constraints should look like in this situation.
clock period = 10 ns
t_setup = 2 ns
t_hold = 0 ns
FYI, the IC I'm trying to interface with is a AD9915 DDS,
(see: http://www.kynix.com/Parts/40239/AD9915BCPZ.html).
It outputs a sync clock that is generated from the internal DDS clock running at much higher frequency using a PLL. The DDS IC then outputs this clock to let upstream devices know when data inputs to the DDS can be updated. The input to the DDS is data only, there is no clock output from the FPGA.
When I try to add an offset constraint directly, i.e.
TIMEGRP "tnm_outs" OFFSET = OUT 5 ns AFTER "clk_in";
the result is that clock path and datapath delays are too long to meet the constraint.
I made a little toy project to isolate the issue. What I see is that even with a FF packed into the IOB, the offset out constraint gives me a timing violation. ISE tells me that the clock path delay is 4.653 ns and the data path delay is 4.301 ns. Timing analysis output from this experiment is attached.
Based on this, I think this is not the right approach. How do the constraints need to look like in this situation?
Thanks a lot for any help in advance!
