macmidi wrote:was not successful in bypassing the switch; will keep trying, however, I think a big clue is that, after getting it to start, unplugging and plugging the power supply does not restart it; I think that would eliminate the switch.
Yeah, I agree that further switch exploration is a waste of time. Probably not my greatest suggestion, anyway.
Don't feel bad about the CZ-101 power circuit. In my opinion, it's
BRUTAL...
There's tons going on there. Lots of interplay and weird bootstrapping stuff that I can't even pretend to understand. Some of this stuff doesn't necessarily apply directly to your problem, but it might help you visualize a few things or give you an idea of what is worth checking and what is not worth checking. Don't take any of it as gospel. I don't understand the CZ-101 very well.
PLACES TO PROBE/MEASURE AND IDEAS TO CONSIDER
APO Switch
The Auto Power Off switch is something that more-or-less enables "sleep mode". Its state is read by the CPU and if the APO switch is on then the CPU shuts the system down after being idle for a set amount of time.
I believe that when people mention APO, they might be conflating it with the low battery detection circuitry. I do not believe the APO switch can ever be a possibility for non-boot / no power type issues because it should be wholly dependent upon a fully booted system. It's really just another button.
'P' Button
Likewise, this gets mentioned sometimes, but don't expect it to do anything. It's just a power-on hotkey which copies a section of ROM into RAM (patch presets which are potentially backed-up by the D-cell batteries) -- no more, no less. Like APO, it's also "just a button" and requires the CPU to be up and running, so doesn't apply unless the CPU is hanging during patch initialization or the like.
M4152-MA2M
Both VBR and VDD are required to power the digital circuitry. If either one is improper then certain parts of the digital circuit aren't going to fire up = no boot.
Find T11 and VR1. See if the emitter of T11 is @ 4.3V when power is off. VR1 can adjust this, if it isn't. This should set the VBR rail.
T4 should output VDD. See what the voltages are at T4. VDD less than 4.75V could be an issue.
M4152-MA1M
VBB is set on this board via VR4, but I believe it only trims analog (audio) voltage in the DAC area, so should be of no consequence here. Only mentioned so no time is spent chasing it.
Of actual importance, however, MA1M does have a detector which powers down on low power. In theory, this shouldn't do anything when running on AC, but look for T1. When battery or AC voltage is >= 6.3V then T1 stays off. When T1 is off then the DETEC line stays high (which is a "good" thing).
When battery or AC voltage is < 6.3V then T1 turns on, consequently DETEC gets dragged to ground and goes low (this is a "bad" thing). The VS line (I'm guessing it stands for Voltage State) represents the actual voltage of the batteries, unlike any of the other regulated rails.
VS is also used by the CPU (AN2 pin) to check the battery voltage in a similar way, except the CPU is already powered on, so the power supply has gone from an acceptable state to a "too low" state after successfully booting. The CPU still has enough power to operate, and will flash the power warning LED and then shut down. This is *not* controlled by, nor the same as, the APO switch.
VR1 in this section (not the same VR1 on MA2M!) adjusts the power off voltage threshold. As mentioned, this is supposed to be set so that T1 changes its state when the power supply dips below or exceeds 6.3V.
I believe all the RESET lines are dependent upon DETEC being set high. No RESET line(s) = no boot.
RESET
On the schematics for M4152-MA1M, look in the middle-left area for the number '10' and letter 'I' which are circled. Right in that area you will see 74HC04 1/6 and 2/6.
74HC04 pin 8 = /RST signal -- It is supposed to dip low then stick high. If you follow the DETEC line, it seems as if DETEC and something in the VDD reset block combine to generate the /RST signal which in turn generates RST1. RST2 appears to be /RST before it gets inverted.
One of the obvious things to do is monitor CPU pin 28 from power-off through power-on. If there's a difference in behavior on that reset signal between successful boot events and non-boot events then backtrack to find out why.
PD
Pd is a power down signal which is output by the CPU. Just like DETEC, it is ordinarily supposed to be high. Pd and DETEC are both present at the 4011 1/4 NAND gate. So VDD has to be stable and high (i.e. a good power supply) for DETEC. DETEC is required for RST. RST is required for the CPU to boot, and the CPU needs to boot before Pd can be controlled.